Programmable logic devices (“PLDs”) are a type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile may include both programmable interconnect and programmable logic. The programmable interconnect may include a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic may be programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices.
In CPLDs, configuration data may be stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs may be programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs may also be implemented in other ways, e.g., using fuse or anti-fuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hardcoded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
PLDs may be used to implement phase interpolators, which can be used to make adjustments to a sampling clock signal. Generally, phase interpolators work by shifting the phase of a sampling clock signal so that it aligns with a received/target clock signal. This allows received data to be sampled at the correct times and/or rates. In some implementations, phase interpolators may operate current mode logic (“CML”), which uses a differential signal to interpolate the sampling clock between two phase angles (e.g., between 0 and 90 degrees).
In current mode logic (“CML”), device mismatch between different components, such as transistors, may cause poor statistical differential non-linearity (“DNL”) at quadrant boundaries when switching from one phase range to another. Accordingly, it may be desirable and useful to improve the statistical DNL at the quadrant boundaries for these types of implementations.